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1/12 july 2001 n high speed : f max = 63 mhz (typ.) at v cc =6v n low power dissipation: i cc =4 m a(max.) at t a =25 c n high noise immunity: v nih =v nil =28%v cc (min.) n symmetrical output impedance: |i oh |=i ol = 4ma (min) n balanced propagation delays: t plh @ t phl n wide operating voltage range: v cc (opr) = 2v to 6v n pin and function compatible with 74 series 166 description the m74hc166 is an high speed cmos 8 bit piso shift register fabricated with silicon gate c 2 mos technology. it consists of parallel or serial inputs and a serial-out 8 bit shift register with gated clock inputs and an overriding clear input. the parallel-in or serial-in modes are controlled by the shift/ load input. when the shift/load input is held high, the serial data input is enabled and the eight flip-flops perform serial shifting with each clock pulse; when held low, the parallel data inputs are enabled and synchronous loading occurs on the next clock pulse. clocking is accomplished on the low-to-high level edge of the clock pulse. the clock-inhibit input should be changed to the high only while the clock input is held high. a direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero. functional details are shown in the truth table and the timing chart. all inputs are equipped with protection circuits against static discharge and transient excess voltage. m74hc166 8 bit piso shift register pin connection and iec logic symbols order codes package tube t & r dip m74hc166b1r sop m74hc166m1r M74HC166RM13TR tssop m74hc166ttr tssop dip sop
m74hc166 2/12 input and output equivalent circuit pin description truth table x : don't care a....... .h : the level of steady input voltage at inputs a through h respectively pin no symbol name and function 1 si serial data inputs 2, 3, 4, 5, 10, 11, 12, 14 a to h parallel data inputs 6 clock inh clock enable input (active low) 7 clock clock input (low to high, edge triggered 9 clear asynchronous master reset input (active low) 13 q h serial output from the last stage 15 shift/load parallel enable input (active low) 8 gnd ground (0v) 16 vcc positive supply voltage inputs internal outputs outputs clear shift/ load clock inh clock serial in parallel a..... .....h qa qb qh lxxxxxlll l x x x x no change h l l x a....... .......h a b h h h l h x h qan qgn h h l l x l qan qgn h x h x x x no change
m74hc166 3/12 logic diagram this logic diagram has not be used to estimate propagation delays timing chart
m74hc166 4/12 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied (*) 500mw at 65 c; derate to 300mw by 10mw/ c from 65 cto85 c recommended operating conditions symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 50 ma p d power dissipation 500(*) mw t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2to6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c t r ,t f input rise and fall time v cc = 2.0v 0 to 1000 ns v cc = 4.5v 0 to 500 ns v cc = 6.0v 0 to 400 ns
m74hc166 5/12 dc specifications symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 v il low level input voltage 2.0 0.5 0.5 0.5 v 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 v oh high level output voltage 2.0 i o =-20 m a 1.9 2.0 1.9 1.9 v 4.5 i o =-20 m a 4.4 4.5 4.4 4.4 6.0 i o =-20 m a 5.9 6.0 5.9 5.9 4.5 i o =-4.0 ma 4.18 4.31 4.13 4.10 6.0 i o =-5.2 ma 5.68 5.8 5.63 5.60 v ol low level output voltage 2.0 i o =20 m a 0.0 0.1 0.1 0.1 v 4.5 i o =20 m a 0.0 0.1 0.1 0.1 6.0 i o =20 m a 0.0 0.1 0.1 0.1 4.5 i o =4.0 ma 0.17 0.26 0.33 0.40 6.0 i o =5.2 ma 0.18 0.26 0.33 0.40 i i input leakage current 6.0 v i =v cc or gnd 0.1 1 1 m a i cc quiescent supply current 6.0 v i =v cc or gnd 44080 m a
m74hc166 6/12 ac electrical characteristics (c l = 50 pf, input t r =t f = 6ns) capacitive characteristics 1) c pd is defined as the value of the ic's internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. t tlh t thl output transition time 2.0 30 75 95 110 ns 4.5 8151922 6.0 7131619 t plh t phl propagation delay time (clock - qh) 2.0 70 150 190 225 ns 4.5 20 30 38 45 6.0 16 26 32 38 t phl propagation delay time (clear - qh) 2.0 60 135 170 205 ns 4.5 18 27 34 41 6.0 14 23 29 35 f max maximum clock frequency 2.0 6.2 14 5.0 4.2 mhz 4.5 31 50 25 21 6.0 37 63 30 25 t w(h) t w(l) minimum pulse width (clock) 2.0 28 75 95 110 ns 4.5 6151922 6.0 5131619 t w(l) minimum pulse width (clear) 2.0 28 75 95 110 ns 4.5 6151922 6.0 5131619 t s minimum set-up time (si, pi) 2.0 20 75 95 110 ns 4.5 4151922 6.0 3131619 t s minimum set-up time (shift/ load) 2.0 25 75 95 110 ns 4.5 5151922 6.0 3131619 t h minimum hold time 2.0 0 0 0 ns 4.5 0 0 0 6.0 0 0 0 t rem minimum removal time 2.0 12 50 65 75 ns 4.5 3101315 6.0 3 9 11 13 symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. c in input capacitance 5.0 5101010pf c pd power dissipation capacitance (note 1) 5.0 60 pf
m74hc166 7/12 test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r t =z out of pulse generator (typically 50 w ) waveform 1 : minimum pulse width (clear), removal time (clear to clock) (f=1mhz; 50% duty cycle)
m74hc166 8/12 waveform 2 : propagation delay time, minimum pulse width (clock), setup and hold time (si to clock) (f=1mhz; 50% duty cycle) waveform 3 : propagation delay time, setup and hold time (pi, s/l to clock) (f=1mhz; 50% duty cycle)
m74hc166 9/12 dim. mm. inch min. typ max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 plastic dip-16 (0.25) mechanical data p001c
m74hc166 10/12 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data po13h
m74hc166 11/12 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 8 0 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
m74hc166 12/12 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this pub lication are subject to change without notice. thi s pub lication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - swit zerland - united kingdom ? http://w ww.st.com

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